1. Field
Example embodiments relate to semiconductor memory devices and methods of fabricating the same, and more particularly, to non-volatile memory devices with improved integration density and methods of fabricating the same.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices that can be electrically programmed and erased. Flash memory devices may have good portability and impact resistance characteristics. There is a growing demand for flash memory devices to be used in portable information devices, such as portable personal computers (PCs) or mobile phones. For this reason, research has been directed towards increasing integration density of memory devices in order to enable the production of increased capacity memory devices. In order to enable increase integration density, flash memory devices were introduced that include 16 or 32 memory cells connected in series to form a string.
As device pitch is reduced in highly integrated flash memory devices, it becomes increasingly difficult to form a contact between an active string and a bit line. The alignment process must be performed very accurately and a defect (e.g., a short circuit) is likely to occur between adjacent bit lines even after forming the contact. A double patterning technology (DPT) process may be performed in order to form bit lines that are accurately aligned in a one to one relationship with an active string within a very small device pitch. However, this process may be difficult to perform.
Furthermore, a reduction of device pitch results in a reduction of the interval between bit lines. A reduction of the interval between bit lines results in an increase in parasitic capacitance because the capacitance is proportional to the surface area of each of the bit lines and is inversely proportional to the distance between the bit lines. When parasitic capacitance CBL-to-BL increases between bit lines the performance of a memory device is degraded. For example, increases or decreases in a read time tread of a memory are directly proportional to increases or decreases in resistance and/or capacitance. Accordingly, methods of preventing parasitic capacitance from increasing due to a reduction in a bit line interval caused by a reduction in device pitch and methods of reducing resistance between a bit line contact and an active region may be desirable.